Independent ground fault detection using current transformer

ABSTRACT

A fault detection system for a system having a single DC input and a plurality of A/C loads such as an electric or hybrid electric vehicle. A plurality of inverters convert DC to 3-phase A/C and supply A/C power to a corresponding individual A/C load. Each inverter includes a common mode current transformer and a controller. An individual corresponding common mode current transformer is coupled to the 3-phase A/C output of the inverter. An individual corresponding controller is coupled to the output of an individual corresponding common mode current transformer and is coupled to an individual corresponding A/C load. Each controller is configured to detect a fault at the individual corresponding A/C load and in the case of detection of a fault at an individual corresponding A/C load, the corresponding controller disables the A/C load.

BACKGROUND

Detection of an A/C ground fault, for example a phase to chassis fault,in the electric drive train and accessory power system of a vehicle hasbeen cause to fault the electric drive/accessory power system as a wholesince there was no clear way to detect which component was compromisedand all components shared a common energy source (DC-Link). This wouldmean that the vehicle would be stranded wherever the fault occurs untilrepairs can be made or the vehicle is towed to a service station. At thevehicle level, the system controller would need to shut down propulsionas well as accessory loads since it could not pinpoint where the faultwas and isolate it.

Typical solutions for this problem involve summing current sensors forall three phases. However the combined error in those sensors in somecases is more than the fault current that would need to be detected.

SUMMARY OF THE INVENTION

In one embodiment, a fault detection system is provided for a systemhaving a single DC input and a plurality of A/C loads. One example ofsuch a system is an electric or hybrid electric vehicle. The faultdetection system in one embodiment of this disclosure includes aplurality of inverters coupled to the DC power source. The plurality ofinverters each convert DC to 3-phase A/C and supply A/C power to acorresponding individual A/C load. The fault detection system includes aplurality of common mode current transformers and a plurality ofcontrollers. An individual corresponding one of the plurality of commonmode current transformers are coupled to the 3-phase A/C output of eachof the plurality of inverters. An individual corresponding one of theplurality of controllers is coupled to the output of an individualcorresponding one of the plurality of common mode current transformersand is coupled to an individual corresponding A/C load. Each of theplurality of controllers is configured to detect a fault at theindividual corresponding A/C load and in the case of detection of afault at an individual corresponding A/C load, the correspondingcontroller disables the A/C load.

In one embodiment, each of the common mode current transformers isconfigured with a primary coil coupled to the 3-phase A/C output of thecorresponding inverter and a secondary coil is coupled to an imbalancedetection circuit of the corresponding controller. A voltage on thesecondary of the common mode current transformer is input to theimbalance detection circuit for fault threshold comparison.

The improvement over prior art solutions is that the disclosed systemcan independently detect and isolate the fault. Independent faultdetection combined with independent inverters allows for detection of afault within a single A/C load and an isolated turn-off of that load sothat the vehicle is able to continue back to the depot for maintenancewithout the use of a road call.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of one embodiment of the system disclosed inthis specification.

FIG. 2 is a schematic diagram of one embodiment of a common mode currenttransformer disclosed in this specification.

FIG. 3 is a block diagram of one embodiment of the inverter disclosed inthis specification.

FIG. 4 is a flow diagram of one embodiment of the method disclosed inthis specification.

FIG. 5 is one embodiment of a modular line replaceable unit disclosed inthis specification.

FIG. 6 is a block diagram of an exemplary computing system suitable forimplementation of the embodiments disclosed in this specification.

Further features as well as the structure and operation of variousembodiments are described in detail below with reference to theaccompanying drawings. In the drawings, like reference numbers indicateidentical or functionally similar elements.

DETAILED DESCRIPTION

In one embodiment, independent inverters are provided for each A/C loadof a system having a single DC input and a plurality of A/C loads. Oneexample of such a system is an electric or hybrid electric vehicle. Anindependent common mode current transformer is connected between the A/Coutput of each inverter and the corresponding A/C load. The common modecurrent transformer is configured with the primary on the high voltage3-phase A/C output and the secondary is input to a controller. Thevoltage of the secondary of the common mode current transformer is inputto the controller for fault threshold comparison. Any imbalance betweenthe phases creates a field which couples to the secondary. In oneembodiment a current from the secondary is detected by the controller asfault current. In one embodiment the current on the secondary isdetected by measuring a voltage across a shunt resistor detected by lowvoltage circuitry of the controller.

FIG. 1 is a schematic diagram of one embodiment of an electric or hybridelectric vehicle control system having independent A/C ground faultdetection. The system 10 includes a system controller 12 and a highvoltage battery pack 14. The system includes several A/C loads 16 thatrequire 3-phase power to operate. The main A/C load is the tractionmotor of the vehicle. Additional A/C loads are the traction generatorand one or more accessories that require A/C power. For example, onesuch A/C accessory is the air conditioning system that has a 3-phasemotor. Shown in FIG. 1 are N A/C loads, 16-1, 16-22 . . . 16-N.

The system 10 includes an independent A/C drive 18 for each A/C load 16.As shown in FIG. 1, A/C drives 18-1, 18-2 . . . 18-N are connectedbetween the system controller 12 and its corresponding A/C load 16-1,16-2 . . . 16-N, respectively. Each A/C drive 18 is connected to thebattery pack 14 by a corresponding DC link 20-1, 20-2 . . . 20-N. TheA/C drives 18 include inverters 22 (22-1, 22-2 . . . 22-N) that converthigh voltage, high current DC from the battery pack 14 to AC and supply3-phase AC power to each A/C load 16. In one embodiment, the inverters22 contain a full bridge switch architecture for the three phases whichputs out square wave A/C power that is fed to the primary winding in atransformer 24 within each of the A/C drives 18. Through the switches,the direction of the flow of current is continuously and regularlyflip-flopped. For example, the electrical charge travels into theprimary winding and load, then abruptly reverses and flows back out. Thein/out flow of electricity produces AC current in the transformer'sprimary winding circuit. This induced alternating current electricityprovides power for the AC load 16. In one embodiment, the A/C drives 18are setup with high and low voltage sections to allow use of low voltageparts where possible. In one embodiment, the A/C drives 18 are comprisedof a logic-level electronic circuit that provides the driving signals topower switches that feed DC, AC, or power signals to a variety of loads,including the A/C loads 16.

In one embodiment, transformer 24 is an independent common mode currenttransformer which is connected between the A/C output of each inverter22 and the corresponding A/C load 16. As shown in FIG. 1, common modecurrent transformers 24-1, 24-2 . . . 24-N are connected between the A/Coutput from the inverters 22-1, 22-2 . . . 22-N of each A/C drive 18 andthe corresponding A/C loads 16-1, 16-2 . . . 16-N, respectively.

As shown in FIG. 2, each of the common mode current transformers 24 isconfigured with the primary 26 on the high voltage 3-phase A/C output ofthe corresponding inverter 18 and the secondary 28 of the common modecurrent transformer 24 is input to a controller 30. All 3 phases passthrough the same common mode current transformer core that has aseparate primary coil 26-A, 26-B and 26-C for each phase. In oneembodiment, the voltage on the secondary 28 is stepped down through aresistor 32 and op-amp 34 to be low voltage so it can be input to thecontroller 30 without damaging the controller. In one embodiment, the3-phase conductors pass through the core with a single turn.

The voltage of the secondary 28 of the common mode current transformer24 is input to the controller 30 for fault threshold comparison. Anyimbalance between the phases creates a field which couples to thesecondary 28 and current from the secondary is detected by thecontroller 30 as fault current. If there is no imbalance in current thenthe current flowing out to one phase cancels with the current comingback from the other two. A current on the secondary 28 is detected bythe controller 30 as a fault current. In one embodiment, the current onthe secondary 28 is detected by measuring a voltage across the shuntresistor 32 detected by low voltage circuitry of the controller 30.

The controller 30 in response to the fault current sends a signal to itscorresponding A/C load 16 to disable the motor of that load. In case ofa fault, the vehicle is able to run without the generator since it hasonboard battery power. The vehicle is also able to run without airconditioning as well as other accessory loads. The only drive that isabsolutely necessary of the traction motor. A fault in the tractionmotor would not result in a disable signal.

The improvement over prior art solutions is that the disclosed systemcan independently detect and isolate the fault. Since all the invertorsand A/C loads are tied to a common DC link input, the system controllerwould need to shutdown the whole link in order to stop the fault if theindependent fault detection of this disclosure was not provided.Independent fault detection combined with independent inverters allowsfor detection of a fault within a single A/C load and an isolatedturn-off of that load so that the vehicle is able to continue back tothe depot for maintenance without the use of a road call.

In one embodiment, each A/C drive 18 includes two circuit cardassemblies (CCA). One CCA 40 includes the controller 30 which has aprocessor with all the program instructions and other intelligence tocontrol the operation of the switches of the inverter 22 on the card.The second CCA 42 is a filter card which has a dV/dT filter circuit 36,the CMCT 24, the shunt resistor 32 and EMI filtering 33. In oneembodiment, as shown in FIG. 3, the dV/dT filter circuit 36 is coupledbetween the common mode current transformer (CMCT) 24 and the inverter22. The dV/dT filter circuit 36 is a device that controls the voltagespikes generated by adjustable frequency drives and long motor leadlengths. As shown in FIG. 3, the dV/dT filter circuit 36 has a separatefilter circuit 36-A, 36-b and 36-C for each phase of the 3-phase A/Cinput from the inverter 22. The controller 30 controls an imbalancedetector circuit 38 which includes the op-amp 34 that is coupled to thesecondary 28 of CMCT 24 through the shunt resistor 32. Any imbalancebetween the phases creates a field which generates a current on thesecondary 28 that is detected by the imbalance detector circuit 38 as afault current. By limiting the number of loads that need to be disabledthe vehicle has a greater chance of being able to return to the servicedepot under its own power and control rather than requiring roadsideservice. Providing each individual load with a separate A/C drive withindependent fault detection provided by the common mode currenttransformer allows the vehicle to not lose all electric drive/accessorypower, this would also be a large advantage in reducing road calls byallowing individual outputs to be disabled instead of disabling theentire electric drive/accessory power system. Limiting the fault to asingle output reduces roadside service calls which limits cost ofownership and enhances customer satisfaction. By being able to isolatethe fault, limit the loss of functionality is limited. For example, ifthe fault was related to an accessory item, then that accessory would beable to be disengaged and in some cases the vehicle would be able toreturn to the service station/depot under its own power.

In addition, fault detection can be measured with higher accuracy thenthe prior art known solutions. By using a common mode currenttransformer (CMCT) the lack of accuracy of the summing operation usingphase current sensors is eliminated. The only accuracy that limits thefault detection is the accuracy with which the transformer outputcurrent is measured. If the CMCT outputs a current then this is onlypossible if a fault exists. In contrast, if an imbalance is seen in thesum of three phase current sensors, it is unclear whether the imbalanceis due to a small chassis fault, or simply the error in the threedifferent phase current sensors. Moreover, since the current rating ofthe phase current sensor often has to be quite large to handle normalphase currents and because the sensor could have several percent of itsfull range in error, this means that these systems can have many amps oferror in the summing operation when using phase current sensors to sumcurrents. In the CMCT system disclosed herein, the only measureablecurrent is fault current so the accuracy with which a fault can bedetected is much higher. This means that the trip point can be muchlower than a current sensor summing method and the issue can be flaggedmuch sooner to the operator. Due to the higher resolution, the CMCTsystem helps protect the hardware faster and to a much finer level.

FIG. 4 is a flow diagram of one embodiment of a fault detection method.The method includes step S1 of converting DC to a 3-phase A/C output tosupply A/C power to a corresponding individual A/C load, step S2 ofproviding a common mode current transformer coupled to the 3-phase A/Coutput, step S3 of detecting an imbalance between the phases as a faultand step S4 of disabling the corresponding individual A/C load inresponse to the detection of a fault.

In one embodiment, as shown in FIG. 5, independent inverters are housedwithin a single line replaceable unit (LRU) 44 for all accessory powerdraws. The accessory power system includes individual D/C loads andindividual A/C loads drawn by various accessory components. In oneembodiment, the LRU 44 is a modular accessory power system that includesup to five DC drive modules 46 and up to five A/C drive modules 48. Inone embodiment, the DC drive modules 46 are individual DC-DC drives thatprovide accessory power control. Each drive 46 provides 28 Vdc at 200 A.In one embodiment, the A/C drive modules are individual DC-AC drivesthat include a DC to AC inverter that provides accessory power input of230 Vac at 28 A rms per drive. A separate common mode currenttransformer is provided in each DC-AC drive module 48. The modularaccessory power system 44 includes a single DC-link input 50.

In one embodiment, the independent drives 46 and 48 may be stackablewithin the housing of LRU 44 to conserve space. As described above, eachDC-AC drive 48 has a common mode current transformer which directlymeasures the imbalance in phase currents and allows fault detection atvery low levels of common mode current. Each individual load has aseparate DC-AC drive 48 with independent fault detection provided by thecommon mode current transformer. This allows an individual drive 48 theability to directly measure common mode current and thereby to detect anissue within itself or the load and disable that individual drive.

FIG. 6 illustrates a schematic of an example computer or processingsystem that may implement the system and method of fault detection inone embodiment of the present disclosure. The computer system is onlyone example of a suitable processing system that may be used toimplement the controller 30 and is not intended to suggest anylimitation as to the scope of use or functionality of embodiments of themethodology described herein. The processing system shown may beoperational with numerous other general purpose or special purposecomputing system environments or configurations. Examples of well-knowncomputing systems, environments, and/or configurations that may besuitable for use with the processing system shown in FIG. 6 may include,but are not limited to, personal computer systems, server computersystems, thin clients, thick clients, handheld or laptop devices,multiprocessor systems, microprocessor-based systems, set top boxes,programmable consumer electronics, network PCs, minicomputer systems,mainframe computer systems, field programmable gate arrays anddistributed cloud computing environments that include any of the abovesystems or devices, and the like.

The components of computer system may include, but are not limited to,one or more processors or processing units 100, a system memory 106, anda bus 104 that couples various system components including system memory106 to processor 100. The processor 100 may include a program module 102that performs the methods described herein. The module 102 may beprogrammed into the integrated circuits of the processor 100, or loadedfrom memory 106, storage device 108, or network 114 or combinationsthereof.

Bus 104 may represent one or more of any of several types of busstructures, including a memory bus or memory controller, a peripheralbus, an accelerated graphics port, and a processor or local bus usingany of a variety of bus architectures. By way of example, and notlimitation, such architectures include Industry Standard Architecture(ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA)bus, Video Electronics Standards Association (VESA) local bus, andPeripheral Component Interconnects (PCI) bus.

The computer system may include a variety of computer system readablemedia. Such media may be any available media that is accessible bycomputer system, and it may include both volatile and non-volatilemedia, removable and non-removable media.

System memory 106 can include computer system readable media in the formof volatile memory, such as random access memory (RAM) and/or cachememory or others. Computer system may further include otherremovable/non-removable, volatile/non-volatile computer system storagemedia. By way of example only, storage system 108 can be provided forreading from and writing to a non-removable, non-volatile magnetic media(e.g., a “hard drive”). Although not shown, a magnetic disk drive forreading from and writing to a removable, non-volatile magnetic disk(e.g., a “floppy disk”), and an optical disk drive for reading from orwriting to a removable, non-volatile optical disk such as a CD-ROM,DVD-ROM or other optical media can be provided. In such instances, eachcan be connected to bus 104 by one or more data media interfaces.

The computer system may also communicate with one or more externaldevices 116 such as a keyboard, a pointing device, a display 118, etc.;one or more devices that enable a user to interact with computer system;and/or any devices (e.g., network card, modem, etc.) that enablecomputer system to communicate with one or more other computing devices.Such communication can occur via Input/Output (I/O) interfaces 110.

Still yet, the computer system can communicate with one or more networks114 such as a local area network (LAN), a general wide area network(WAN), and/or a public network (e.g., the Internet) via network adapter112. As depicted, network adapter 112 communicates with the othercomponents of computer system via bus 104. It should be understood thatalthough not shown, other hardware and/or software components could beused in conjunction with computer system. Examples include, but are notlimited to: microcode, device drivers, redundant processing units,external disk drive arrays, RAID systems, tape drives, and data archivalstorage systems, etc.

Various embodiments may be implemented using hardware elements, softwareelements, or a combination of both. Examples of hardware elements mayinclude processors, microprocessors, circuits, circuit elements (forexample, transistors, resistors, capacitors, inductors, and so forth),integrated circuits, ASICs, programmable logic devices, digital signalprocessors, FPGAs, logic gates, registers, semiconductor devices, chips,microchips, chipsets, and so forth. Examples of software may includesoftware components, programs, applications, computer programs,application programs, system programs, machine programs, operatingsystem software, middleware, firmware, software modules, routines,subroutines, functions, methods, procedures, software interfaces,application program interfaces, instruction sets, computing code,computer code, code segments, computer code segments, words, values,symbols, or any combination thereof. Determining whether an embodimentis implemented using hardware elements and/or software elements may varyin accordance with any number of factors, such as desired computationalrate, power level, heat tolerances, processing cycle budget, input datarates, output data rates, memory resources, data bus speeds, and otherdesign or performance constraints.

Some embodiments may be described using the expression “coupled” and“connected” along with their derivatives. These terms are not intendedas synonyms for each other. For example, some embodiments may bedescribed using the terms “connected” and/or “coupled” to indicate thattwo or more elements are in direct physical or electrical contact witheach other. The term “coupled,” however, may also mean that two or moreelements are not in direct contact with each other, but yet stillcooperate or interact with each other.

The various embodiments disclosed herein can be implemented in variousforms of hardware, software, firmware, and/or special purposeprocessors. For example, in one embodiment at least one non-transitorycomputer readable storage medium has instructions encoded thereon that,when executed by one or more processors, cause one or more of thenetwork address configuration methodologies disclosed herein to beimplemented. The instructions can be encoded using a suitableprogramming language, such as C, C++, object oriented C, Java,JavaScript, Visual Basic .NET, Beginner's All-Purpose SymbolicInstruction Code (BASIC), or alternatively, using custom or proprietaryinstruction sets. The instructions can be provided in the form of one ormore computer software applications and/or applets that are tangiblyembodied on a memory device, and that can be executed by a computerhaving any suitable architecture. In one embodiment, the system can behosted on a given website and implemented, for example, using JavaScriptor another suitable browser-based technology. For instance, in certainembodiments, the system may leverage processing resources provided by aremote computer system accessible via network. The computer softwareapplications disclosed herein may include any number of differentmodules, sub-modules, or other components of distinct functionality, andcan provide information to, or receive information from, still othercomponents. These modules can be used, for example, to communicate withinput and/or output devices such as a display screen, a touch sensitivesurface, a printer, and/or any other suitable device. Other componentsand functionality not reflected in the illustrations will be apparent inlight of this disclosure, and it will be appreciated that otherembodiments are not limited to any particular hardware or softwareconfiguration. Thus in other embodiments system may comprise additional,fewer, or alternative subcomponents as compared to those included in theexample embodiments.

The aforementioned non-transitory computer readable medium may be anysuitable medium for storing digital information, such as a hard drive, aserver, a flash memory, and/or random access memory (RAM), or acombination of memories. In alternative embodiments, the componentsand/or modules disclosed herein can be implemented with hardware,including gate level logic such as a field-programmable gate array(FPGA), or alternatively, a purpose-built semiconductor such as anapplication-specific integrated circuit (ASIC). Still other embodimentsmay be implemented with a microcontroller having a number ofinput/output ports for receiving and outputting data, and a number ofembedded routines for carrying out the various functionalities disclosedherein. It will be apparent that any suitable combination of hardware,software, and firmware can be used, and that other embodiments are notlimited to any particular system architecture.

Some embodiments may be implemented, for example, using a machinereadable medium or article which may store an instruction or a set ofinstructions that, if executed by a machine, may cause the machine toperform a method and/or operations in accordance with the embodimentsdisclosed herein. Such a machine may include, for example, any suitableprocessing platform, computing platform, computing device, processingdevice, computing system, processing system, computer, process, or thelike, and may be implemented using any suitable combination of hardwareand/or software. The machine readable medium or article may include, forexample, any suitable type of memory unit, memory device, memoryarticle, memory medium, storage device, storage article, storage medium,and/or storage unit, such as memory, removable or non-removable media,erasable or non-erasable media, writeable or rewriteable media, digitalor analog media, hard disk, floppy disk, compact disk read only memory(CD-ROM), compact disk recordable (CD-R) memory, compact diskrewriteable (CR-RW) memory, optical disk, magnetic media,magneto-optical media, removable memory cards or disks, various types ofdigital versatile disk (DVD), a tape, a cassette, or the like. Theinstructions may include any suitable type of code, such as source code,compiled code, interpreted code, executable code, static code, dynamiccode, encrypted code, and the like, implemented using any suitable highlevel, low level, object oriented, visual, compiled, and/or interpretedprogramming language.

Unless specifically stated otherwise, it may be appreciated that termssuch as “processing,” “computing,” “calculating,” “determining,” or thelike refer to the action and/or process of a computer or computingsystem, or similar electronic computing device, that manipulates and/ortransforms data represented as physical quantities (for example,electronic) within the registers and/or memory units of the computersystem into other data similarly represented as physical quantitieswithin the registers, memory units, or other such information storagetransmission or displays of the computer system. The embodiments are notlimited in this context.

The terms “circuit” or “circuitry,” as used in any embodiment herein,are functional and may comprise, for example, singly or in anycombination, hardwired circuitry, programmable circuitry such ascomputer processors comprising one or more individual instructionprocessing cores, state machine circuitry, and/or firmware that storesinstructions executed by programmable circuitry. The circuitry mayinclude a processor and/or controller configured to execute one or moreinstructions to perform one or more operations described herein. Theinstructions may be embodied as, for example, an application, software,firmware, etc. configured to cause the circuitry to perform any of theaforementioned operations. Software may be embodied as a softwarepackage, code, instructions, instruction sets and/or data recorded on acomputer-readable storage device. Software may be embodied orimplemented to include any number of processes, and processes, in turn,may be embodied or implemented to include any number of threads, etc.,in a hierarchical fashion. Firmware may be embodied as code,instructions or instruction sets and/or data that are hard-coded (e.g.,nonvolatile) in memory devices. The circuitry may, collectively orindividually, be embodied as circuitry that forms part of a largersystem, for example, an integrated circuit (IC), an application-specificintegrated circuit (ASIC), a system on-chip (SoC), desktop computers,laptop computers, tablet computers, servers, smart phones, etc. Otherembodiments may be implemented as software executed by a programmablecontrol device. In such cases, the terms “circuit” or “circuitry” areintended to include a combination of software and hardware such as aprogrammable control device or a processor capable of executing thesoftware. As described herein, various embodiments may be implementedusing hardware elements, software elements, or any combination thereof.Examples of hardware elements may include processors, microprocessors,circuits, circuit elements (e.g., transistors, resistors, capacitors,inductors, and so forth), integrated circuits, application specificintegrated circuits (ASIC), programmable logic devices (PLD), digitalsignal processors (DSP), field programmable gate array (FPGA), logicgates, registers, semiconductor device, chips, microchips, chip sets,and so forth.

Numerous specific details have been set forth herein to provide athorough understanding of the embodiments. It will be understood by anordinarily-skilled artisan, however, that the embodiments may bepracticed without these specific details. In other instances, well knownoperations, components and circuits have not been described in detail soas not to obscure the embodiments. It can be appreciated that thespecific structural and functional details disclosed herein may berepresentative and do not necessarily limit the scope of theembodiments. In addition, although the subject matter has been describedin language specific to structural features and/or methodological acts,it is to be understood that the subject matter defined in the appendedclaims is not necessarily limited to the specific features or actsdescribed herein. Rather, the specific features and acts describedherein are disclosed as example forms of implementing the claims.

The terms and expressions which have been employed herein are used asterms of description and not of limitation, and there is no intention,in the use of such terms and expressions, of excluding any equivalentsof the features shown and described (or portions thereof), and it isrecognized that various modifications are possible within the scope ofthe claims. Accordingly, the claims are intended to cover all suchequivalents. Various features, aspects, and embodiments have beendescribed herein. The features, aspects, and embodiments are susceptibleto combination with one another as well as to variation andmodification, as will be understood by those having skill in the art.The present disclosure should, therefore, be considered to encompasssuch combinations, variations, and modifications. It is intended thatthe scope of the present disclosure not be limited by this detaileddescription, but rather by the claims appended hereto. Future filedapplications claiming priority to this application may claim thedisclosed subject matter in a different manner, and may generallyinclude any set of one or more elements as variously disclosed orotherwise demonstrated herein.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

What is claimed is:
 1. A fault detection system comprising: a DC powersource; a plurality of inverters coupled to the DC power source, theplurality of inverters converting DC to 3-phase A/C, the plurality ofinverters each supplying A/C power to a corresponding individual A/Cload; a plurality of common mode current transformers, an individualcorresponding one of the plurality of common mode current transformersbeing coupled to the 3-phase A/C output of each of the plurality ofinverters; and a plurality of controllers, an individual correspondingone of the plurality of controllers being coupled to the output of anindividual corresponding one of the plurality of common mode currenttransformers and being coupled to an individual corresponding A/C load,each of the plurality of controllers being configured to detect a faultat the individual corresponding A/C load, wherein in the case ofdetection of a fault at an individual corresponding A/C load, thecorresponding controller disables the A/C load.
 2. The fault detectionsystem of claim 1, wherein each of the common mode current transformersis configured with a primary coil coupled to the 3-phase A/C output ofthe corresponding inverter and a secondary coil coupled to an imbalancedetection circuit of the corresponding controller, wherein a current onthe secondary of the common mode current transformer is input to theimbalance detection circuit for fault threshold comparison.
 3. The faultdetection system of claim 2, wherein each of the common mode currenttransformers has a separate primary coil for each phase of the 3-phaseA/C output of the corresponding inverter.
 4. The fault detection systemof claim 2, wherein the current on the secondary of the common modecurrent transformer is measured as voltage across a high precisionresistor using an op amp to input a low voltage to the correspondingcontroller.
 5. The fault detection system of claim 1, each of theplurality of inverters includes a dV/dT filter circuit coupled to thecorresponding common mode current transformer.
 6. A line replaceableunit comprising: a DC link input configured to be coupled to DC powersource; a plurality of DC drive modules coupled to the DC link input;and a plurality of DC-AC drive modules coupled to the DC link input,each DC-AC drive module comprising: an inverter coupled to the DC linkinput, the inverter converting DC to 3-phase A/C to supply A/C power toa corresponding individual A/C load; a common mode current transformercoupled to the 3-phase A/C output of the inverter; and a controllercoupled to the output of the common mode current transformer and coupledto the corresponding A/C load, the plurality of controller beingconfigured to detect a fault at the individual corresponding A/C load,wherein in the case of detection of a fault at the individualcorresponding A/C load, the controller disables the corresponding A/Cload.
 7. The line replaceable unit of claim 6, wherein the common modecurrent transformer is configured with a primary coil coupled to the3-phase A/C output of the inverter and a secondary coil coupled to animbalance detection circuit of the controller, wherein a current on thesecondary of the common mode current transformer is input to theimbalance detection circuit for fault threshold comparison.
 8. The linereplaceable unit of claim 7, wherein the common mode current transformerhas a separate primary coil for each phase of the 3-phase A/C output ofthe inverter.
 9. A fault detection method comprising: converting DC to3-phase A/C output to supply A/C power to a corresponding individual A/Cload; providing a common mode current transformer coupled to the 3-phaseA/C output; detecting an imbalance between the phases as a fault; anddisabling the corresponding individual A/C load in response to thedetection of a fault.
 10. The method of claim 9, wherein the common modecurrent transformer is configured with a primary coil coupled to the3-phase A/C output and a secondary coil coupled to an imbalancedetection circuit of a controller, wherein a current on the secondary ofthe common mode current transformer is input to the imbalance detectioncircuit for fault threshold comparison.
 11. The method of claim 10,wherein a current from the secondary of the common mode currenttransformer is detected as a voltage on a shunt resistor by thecontroller as a fault.
 12. A computer system for detecting a fault,comprising: one or more computer processors; one or more non-transitorycomputer-readable storage media; program instructions, stored on the oneor more non-transitory computer-readable storage media, which whenimplemented by the one or more processors, cause the computer system toperform the steps of: converting DC to 3-phase A/C to supply A/C powerto a corresponding individual A/C load; providing a common mode currenttransformer coupled to the 3-phase A/C output of the inverter; detectingan imbalance between the phases as a fault; and disabling thecorresponding individual A/C load in response to the detection of afault.
 13. The computer system of claim 12, wherein the common modecurrent transformer is configured with a primary coil coupled to the3-phase A/C output of the inverter and a secondary coil coupled to animbalance detection circuit of a controller, wherein a current on thesecondary of the common mode current transformer is input to theimbalance detection circuit for fault threshold comparison.
 14. Acomputer program product comprising: program instructions on acomputer-readable storage medium, where execution of the programinstructions using a computer causes the computer to perform a methodfor detecting a fault, comprising: converting DC to 3-phase A/C tosupply A/C power to a corresponding individual A/C load; providing acommon mode current transformer coupled to the 3-phase A/C output of theinverter; detecting an imbalance between the phases as a fault; anddisabling the corresponding individual A/C load in response to thedetection of a fault.
 15. The computer program product of claim 14,wherein the common mode current transformer is configured with a primarycoil coupled to the 3-phase A/C output of the inverter and a secondarycoil coupled to an imbalance detection circuit of a controller, whereina current on the secondary of the common mode current transformer isinput to the imbalance detection circuit for fault threshold comparison.